The present invention relates in general to substrate manufacturing technologies and in particular to methods and apparatus for the optimization of highly selective process gases in order to etch a barrier layer.
In the processing of a substrate, e.g., a semiconductor substrate or a glass panel such as one used in flat panel display manufacturing, plasma is often employed. As part of the processing of a substrate for example, the substrate is divided into a plurality of dies, or rectangular areas, each of which will become an integrated circuit. The substrate is then processed in a series of steps in which materials are selectively removed (etching) and deposited (deposition) in order to form electrical components thereon.
In an exemplary plasma process, a substrate is coated with a thin film of hardened emulsion (i.e., such as a photoresist mask) prior to etching. Areas of the hardened emulsion are then selectively removed, causing components of the underlying layer to become exposed. The substrate is then placed in a plasma processing chamber on a substrate support structure comprising a mono-polar or bi-polar electrode, called a chuck or pedestal. Appropriate etchant source are then flowed into the chamber and struck to form a plasma to etch exposed areas of the substrate.
FIG. 1 depicts a plasma processing system 150 including a chamber 100 equipped with a pump 120 to maintain a low chamber pressure and exhaust the process gas effluent. Chamber 100 is grounded as is the upper electrode 104 that also acts as a showerhead type gas distribution system. RF power is supplied from power source 101 to an electrostatic chuck (chuck) 108 situated on a lower electrode assembly 106. RF power source may include a means for matching to the plasma impedance by frequency tuning or by tuning a variable impedance in matching network 145. Plasma 102 is generated by supplying RF power to chuck 108 in order to process substrate 109. In this example system, plasma 102 is confined between chuck 108 and electrode 104 by means of confinement rings 103, which may control a pressure within plasma 102. Confinement rings 103 can be moved to increase and decrease a spacing or gap between adjacent confinement rings, commonly by the use of cam ring. Gas distribution system 122 is commonly comprised of compressed gas cylinders containing plasma processing gases (e.g., C4F8, C4F6, CHF3, CH3F, CF4, HBr, CH3F, C2F4, N2, O2, Ar, Xe, He, H2, NH3, SF6, BCl3, Cl2, WF6, etc).
Generally, some type of cooling system is coupled to the chuck in order to achieve thermal equilibrium once the plasma is ignited. The cooling system itself is usually comprised of a chiller that pumps a coolant through cavities in within the chuck, and helium gas pressurizes the small gap between the chuck and the substrate. In addition to removing the generated heat, the helium gas also allows the cooling system to rapidly control heat dissipation. That is, increasing helium pressure subsequently also increases the heat transfer rate. Most plasma processing systems are also controlled by sophisticated computers comprising operating software programs. In a typical operating environment, manufacturing process parameters (e.g., voltage, gas flow mix, gas flow rate, pressure, etc.) are generally configured for a particular plasma processing system and a specific recipe.
In a common substrate manufacturing method, known as dual damascene, dielectric layers are electrically connected by a conductive plug filling a via hole. Generally, an opening is formed in a dielectric layer, usually lined with a barrier material (e.g. SiCN, SiC, SiON, Si3N4, etc.), and then subsequently filled with a conductive material (e.g., aluminum (Al), copper (Cu), etc.) that allows electrical contact between two sets of conductive patterns. This establishes electrical contact between two active regions on the substrate, such as a source/drain region. Excess conductive material on the surface of the dielectric layer is typically removed by chemical mechanical polishing (CMP). A blanket layer of barrier dielectric film (e.g., silicon nitride, SiC, or SiCN) is then deposited to cap the copper.
There are generally two commonly used approaches for manufacturing dual damascene substrate: via-first and trench-first. In one example of the via-first methodology, the substrate is first coated with photoresist and then the vias are lithographically patterned. Next, an anisotropic etch cuts through the surface cap material and etches down through the low-k layer of the substrate, and stops on the barrier material, just above the underlying metal layer. Next, the via photoresist layer is stripped, and the trench photoresist is applied and lithographically patterned. Typically, some of the photoresist will remain in the bottom of the via, or the via may be covered by an organic ARC plug, in order to prevent the lower portion via from being over-etched during the trench etch process. A second anisotropic etch then cuts through the surface cap material and etches the low-k material down to a desired depth. This etch forms the trench. The photoresist is then stripped and the barrier material at the bottom of the via is opened with a very soft, low-energy power etch that will not cause the underlying copper to sputter into the via sidewall or to minimize copper surface damage. As described above, the trench and via are filled with a conductive material (e.g., aluminum (Al), Copper (Cu), etc.) and polished by chemical mechanical polishing (CMP).
An alternate methodology is trench-first. In one example, the substrate is coated with photoresist and a trench lithographic pattern is applied. An anisotropic dry etch then cuts through the surface hard mask (e.g., SiCN, SiC, SiON, Si3N4, etc.) followed by stripping the photoresist. Another photoresist is applied over the trench hard mask and then the vias are lithographically patterned. A second anisotropic etch then cuts through cap layer and partially etches down into the low-k material. This etch forms the partial vias. The photoresist is then stripped for trench etch over the vias with the hard mask. The trench etch then cuts through the cap layer and partially etches the low-k material down to desired depth. This etch also clears via holes at the same time stopping on the final barrier material located at the bottom of the via. The final barrier material may then be opened with a special etch.
To facilitate discussion, FIG. 2A illustrates an idealized cross-sectional view of the layer stack, representing the layers of an exemplar substrate, prior to a lithographic step. In the discussions that follow, terms such as “above” and “below,” which may be employed herein to discuss the spatial relationship among the layers, may, but need not always, denote a direct contact between the layers involved. It should be noted that other additional layers above, below, or between the layers shown may be present. Further, not all of the shown layers need necessarily be present and some or all may be substituted by other different layers.
At the bottom of the layer stack, there is shown a layer 208, comprising a dielectric film above the contacts and semi-conductor gates. Above layer 208 is deposited a barrier layer 204 (e.g. SiCN, SiC, SiON, Si3N4, etc.). Dual damascene substrates further comprise a set of metal layers including M1 209a-b, typically comprising aluminum or copper. Above the barrier layer 204, is deposited an intermediate dielectric (IMD) layer 206, comprising a low-k material (e.g., SiOC, black diamond, coral, etc.). Above the IMD layer 206, there may be placed a cap layer 203, typically comprising SiCN, SiC, or SiO2. Above cap layer 203, there may be disposed a trench mask layer 202, typically comprising TiN, SiN, or TaN.
Examples of CVD Organosilicate Glass (OSG) low-k material include:
SupplierNamek valueApplied MaterialsBlack Diamond ™ 3.1-2.4Novellus SystemsCORAL ™2.85-2.2Trikon TechnologiesFlowfill ™ (non-porous)2.8ORION ™ (porous)2.2ASMAurora<3.0Dow CorningSiCOH2.7
Examples of Spin-On Dielectric (SOD) low-k material include:
SupplierNamek valueShipleyZirkon2.25Dow ChemicalSiLK (non-porous)2.65p-SiLK (porous)<2.4JSRLKD-5109 (porous)2.2HoneywellNanoglass (porous)2.2-1.9
FIG. 2B shows a somewhat idealized cross-sectional view of the layer stack of FIG. 2A, after photoresist layer 220 and a BARC layer 212 is further added.
FIG. 2C shows a somewhat idealized cross-sectional view of the layer stack of FIG. 2B after photoresist layer 220 and etched BARC layer 212 have been processed through lithography and plasma etch respectively. In this example, a photoresist mask pattern is created with a set of trenches 214a-b. 
FIG. 2D shows the cross-sectional view of the layer stack of FIG. 2C after trench mask layer 201 has been processed in the plasma system, further extending trench 214a-b to cap layer 203.
FIG. 2E shows the cross-sectional view of the layer stack of FIG. 2D, after photoresist layer 220 and a BARC layer 212 are removed.
FIG. 2F shows the cross-sectional view of the layer stack of FIG. 2E after a second photoresist layer 216 and a BARC layer 218 are disposed, in order to create a second metal layer and a via connecting it to the first metal layer 209a-b. 
FIG. 2G shows the cross-sectional view of the layer stack of FIG. 2F after the photoresist mask and BARC layers have been opened and an etch has been performed to partially etch into IMD layer 206 to create a via.
FIG. 2H shows the cross-sectional view of the layer stack of FIG. 2G after photoresist layer 216 and BARC layer 218 have been stripped, and an additional etch process has been performed to extend the trench to a desired depth and etch through a via stopping on barrier layer 204.
In FIG. 2I, the barrier layer 204 is etched through using, for example CH2F2, CH3F, etc.
In FIG. 2J, a chemical mechanical polish process has been performed to polish the layer stack down to cap layer 203, and a conductive material (e.g., aluminum (Al), Copper (Cu), etc.) has been deposited to contact the existing M1 metal material.
In general, as substrate interconnect dimensions continue to shrink, on-chip resistance-capacitance (RC) time delays become the major limitation in achieving faster circuit speeds. In order to reduce the time delays, low dielectric constant materials are commonly used. However, materials with low dielectric constants may also be susceptible to chemical modifications in aggressive environments, such as during etch and resist strip.
Consequently, determining when to stop the process (endpoint) may be critical. Endpoint generally refers to a set of values, or a range, in a plasma process (e.g., time) for which a process is considered complete. For example, when etching a via, it is important to determine when a barrier layer (e.g, SiCN, SiC, SiON, Si3N4, etc.) has been substantially penetrated, in order minimize the amount of etching into the underlying layer.
However, with these and other plasma processes, it is often difficult to monitor the process since process conditions may be dynamic within a plasma processing system because of chamber residue build up, plasma damage to chamber structures, etc. In general, etchants used to etch the barrier layer do not have a high selectivity to the exposed low-k layer, and hence may substantially damage the low-k layer if not stopped and the appropriate time. Selectivity is generally the ratio of the etch rates between different materials, particularly the material that needs to be etched compared with the material that should not be etched.
One common technique used in plasma processing systems is optical emission spectroscopy (OES). In OES, an optical emission from a set of selected chemical species (i.e., such as radicals, ions, etc.) in a plasma processing system may be correlated to a process threshold, such as endpoint. That is, each type of activated species within the plasma processing chamber generally possesses a unique spectral signature, usually corresponding to a unique set of electromagnetic radiation wavelengths (usually between about 245 nm to about 800 nm). By monitoring for the intensity of a specific wavelength not substantially produced by any other species or by the plasma process itself, a process threshold can be determined by observing a change in the relative amount of a specific species in the plasma chamber.
For example, when SiCN is etched with a CF-based etchant, an N species is generally produced with a specific wavelength of about 674 nm. Once substantially consumed, the corresponding wavelength of the produced species generally drops, signaling that the process has achieved endpoint.
However, current optical spectrometry endpoint detection methods tend to be sensitive to changes in the chamber conditions, and hence may be inaccurate. For example, if the proper endpoint is not determined, the process gas may substantially etch into and hence damage the low-k layer. In some instances these changes in the plasma optical emissions can be comparable to an expected change used to trigger an endpoint call, thus causing a false endpoint call to occur. In addition, since only a small fraction of the total surface area (generally less than about 1%) may actually produce a signal change at endpoint, the change may be difficult to detect in the presence of the background chamber OES signal. Furthermore, effective mission spectral analysis is also made more difficult by the escalating requirements for substrates with sub-micron via contacts and high aspect ratios.
A possible solution is to reduce the etch rate in order to minimize the potential damage to the low-k material, assuming that the particular optical spectrometry endpoint detection method used may still detect a measured endpoint that is reasonably close to the actual endpoint. However, as the etching process tends to have complex interrelationships between physical, chemical, and electrical parameters, reducing the etch rate may adversely affect other aspects of the plasma process. For example, as etch rate slowed, feature profiles may be distorted, or mask undercut or roughness may be aggravated.
Referring now to FIG. 3, a simplified view of an etch process is shown. In general, a plasma etch process is substantially complex, and influenced by many factors. For example, an RF field creates several types species in plasma 310, such as high energy electrons, positive ions, negative ions, neutrals, and radicals. Positive ions are created when an electron is completely removed from a gas molecule or atom. Likewise, negative ions although rare, are created when an electron is added to a gas molecule or atom.
Radicals are created when electron collisions break up molecules into fragments which as a result have unsatisfied chemical bonding and are chemically reactive. Since they have no net charge, and therefore are not accelerated by the field or are not attracted by charged particles, they tend have a long lifetime compared to charged particles. Neutrals are stable, having neither a positive nor negative charge, nor are chemically active. Generally, two of the most important parameters are the number density and energy distribution of the electrons, which play a central role in initiating and maintaining the plasma.
In general, in a plasma etch process, directional etching is achieved by sidewall passivation, often through polymer formation 324 on the etch front. The amount of sidewall passivation depends on the amount of etch product and mask area, and it changes dramatically as one moves from isolated features to densely populated portions of the integrated circuit. The amount of sidewall passivation material determines the profile of the structure.
Some of the reactants in the plasma are transported to the substrate surface 302, where reaction 301 may occur, such as physi-sorption or chemisorption 304. In chemisorption, a strong “chemical bond” is formed between the adsorbed atom or molecule and the substrate. Physisorption is weaker, and is often being considered as having no chemical interaction involved.
Other reactants may then be transported to etch front 314, or deflected away if composed of ions 308. In combination with substrate temperature control 316 and bias created 318, these factors may subsequently affect profile 310 and surface quality 312. As previously described, ions are often used in etch reaction 320 to physically dislodged material from the substrate (e.g., oxide, etc.), while neutrals and radicals may be used in a etch reaction 320 to chemically remove material from the substrate. Reaction by-products often diffuse back into the main plasma gas stream and may be subsequently pumped 328 from plasma chamber 330.
Referring now to FIG. 4, a simplified diagram comparing selectivity to RF power in a plasma etch process is shown. All other plasma process characteristics held constant, in general, increasing RF power reduces the etch selectivity of barrier material to IMD film since the etch process tends to be more physical (i.e., sputtering) and less chemical. As previously described, selectivity is the ratio of the etch rates between the different materials, especially the material that needs to be etched compared with the material that should not be removed.
Referring now to FIG. 5, a simplified diagram comparing selectivity to pressure in a plasma etch process is shown. In contrast to FIG. 4, all other plasma process characteristics held constant, in general, increasing pressure tends to increase the etch selectivity of barrier material to IMD film, since the plasma, saturated with ions, has a smaller MFP. Since fewer ions are available to reach the substrate surface, the etch process tends to be less physical and more chemical.
In view of the foregoing, there are desired methods and apparatus for the optimization of highly selective process gases in order to etch through a barrier layer across a large process window.